This invention relates in general to built-in self test circuits and, more particularly, to a combined data generator and data analyzer for built-in self test applications.
In many circuit designs, especially application specific integrated circuits (ASIC), it is desirable to include a built-in self test (BIST) feature in the architecture to allow efficient testing during manufacturing and later for in-service field checks. Some of the advantages of BIST circuit design include efficiency of testing in that the manufacturer need not incur the time and expense of building dedicated test fixtures to preform functional and operational checks of the circuit under test. The BIST circuits are located within the integrated circuit (IC) and therefore become activated by an external control signal to functionally test the circuit. Moreover, BIST circuits allow the circuit under test to be verified at normal operating speeds for the IC, say 50 MHz, whereas multipurpose commercial IC testers typically operate at 1 MHz.
A disadvantage of the BIST approach is the physical area of the IC which must be allocated for the BIST circuit elements, leaving less space for normal functional components. Thus, the advantages and features available with a BIST circuit on-chip must be balanced against the loss of physical area in the IC otherwise useable for normal functional features.
Hence, what is needed is an improved BIST circuit using a minimal amount of the available IC area.